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Tanner EDA tools for analog and mixed-signal ICs and MEMS design offers designers a seamless, efficient path from design capture through verification. Our powerful, robust tool suite is ideal for applications including Power Management, Life Sciences / Biomedical, Displays, Image Sensors, Automotive, Aerospace, RF, Photovoltaics, Consumer Electronics and MEMS.
Front End Tools:
HiPer Simulation
HiPer Simulation, Tanner EDA's design entry and simulation system includes S-Edit for schematic capture, T-Spice for circuit simulation and W-Edit for waveform viewing and analysis. T-Spice is HSPICE and Pspice compatible and supports the latest industry models; including Verilog-A for behavioral modeling.
HiPer Simulation AFS
HiPer Simulation AFS adds Analog FastSPICE capability from BDA (Berkeley Design Automation) to Tanner's HiPer Simulation tool suite. It includes schematic capture (S-Edit), circuit simulation (T-Spice with Verilog-A), Analog FastSPICE (T-AFS), and waveform viewing and analysis (W-Edit).
Tanner Analog FastSPICE (T-AFS) licenses may be purchased as tokens; allowing the user several options on how to best allocate the tool to their workload. Transient noise analysis can also be performed by purchasing a TNA token.
Click here to learn more about T-AFS
HiPer Simulation AMS
HiPer Simulation AMS is a complete mixed signal IC design front-end. Includes schematic capture (S-Edit), analog simulation (T-Spice), digital simulation (Aldec Riviera Pro TE), mixed signal simulation (Verilog-AMS co-simulation), and waveform viewing and analysis (W-Edit).
Click here to learn more about HiPer Simulation AMS
T-Spice Pro
T-Spice Pro from Tanner EDA offers front-end designers industry-leading productivity and price-performance by combining our Schematic Capture tool (S-Edit), our Waveform viewing and analysis tool (W-Edit), and our circuit simulator (T-Spice). Additional simulation capacity can be added; by purchasing stand-alone T-Spice licenses and/or by adding T-AFS; BDA�s Analog FastSPICE.
T-Spice Power Packs
For users looking to augment their simulation capabilities and increase productivity through simultaneous simulation runs, Tanner EDA offers add-on packs of our T-Spice simulation engine. Available in units of 1, 3, 5, and 10 additional licenses, this power pack significantly bolsters productivity and reduces analysis time.
Back End Tools:
L-Edit
L-Edit combines industry-leading rendering speed with powerful features and an elegant user interface that delivers unmatched productivity in physical layout. Drawing and editing are done quickly; with fewer keystrokes and mouse clicks than other layout tools. Powerful features such as object snapping, boolean operations, and alignment tools work within an intuitive user interface so you can work efficiently and effectively.
L-Edit IC
Based on L-Edit, the fastest rendering layout editor in the market, L-Edit IC is a comprehensive physical layout and verification system that accelerates design cycles with high performance and an extremely short learning curve. L-Edit IC includes Interactive Design Rule Checking (IDRC), Node Highlighting, Schematic-Driven Layout, I/O pad cross-reference export, and our Standard Device Generator.
HiPer L-Edit DevGen
HiPer L-Edit DevGen is for engineers looking to gain high productivity by accelerating the task of creating analog building blocks such as differential pairs, current mirrors, and MOSFETs. This package couples our high-performance L-Edit IC package with HiPer DevGen. Click here to learn more about this high-performance layout acceleration capability.
HiPer L-Edit Router
HiPer L-Edit Router combines our high-performance L-Edit IC package with our SDL Router, a general area based router ideal for top-level chip assembly; offering unparalleled workflow productivity for engineers doing layout routing.
HiPer Place & Route (P&R)
HiPer Place & Router (P&R) is a right-size place and route solution for Big Analog/Little Digital mixed-signal design, offering excellent performance, ease of use, and value. HiPer P&R is optimized for analog specialty process technologies on the 90-350nm nodes, with 10-50k gates of digital logic. HiPer P&R is highly flexible, allowing the user unparalleled flexibility during every phase of the flow.
Physical Verification:
HiPer Verify
HiPer Verify from Tanner EDA is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and netlist extraction on the Windows and Linux platforms. HiPer Verify uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs. HiPer Verify can run Calibre and Dracula rule files directly from the foundry; offering the security of knowing you are running your rule files without modification or conversion, as well as the convenience of not having to perform translations.
Click here to view the HiPer Verify datasheet
External Verification Interface (EVI) for Calibre Integration
External Verification Interface (EVI) provides an interface for users of Mentor Graphics' Calibre� tool suite to use L-Edit and S-Edit for layout and schematic capture. Used in conjunction with the Calibre RVE product, you can view Calibre DRC errors, LVS results, and PEX parasitics in L-Edit and S-Edit.
EVI is also compatible with Calibre Interactive, which allows users to run DRC & LVS on L-Edit and S-Edit designs from within Calibre Interactive.
Parasitic Extraction
HiPer PX, Tanner EDA's parasitic extraction system, ensures successful RF IC tapeouts by providing accurate, simulation-ready RC models of interconnect parasitics and crosstalk.
Front End Tools:
HiPer Simulation
HiPer Simulation, Tanner EDA's design entry and simulation system includes S-Edit for schematic capture, T-Spice for circuit simulation and W-Edit for waveform viewing and analysis. T-Spice is HSPICE and Pspice compatible and supports the latest industry models; including Verilog-A for behavioral modeling.
HiPer Simulation AFS
HiPer Simulation AFS adds Analog FastSPICE capability from BDA (Berkeley Design Automation) to Tanner's HiPer Simulation tool suite. It includes schematic capture (S-Edit), circuit simulation (T-Spice with Verilog-A), Analog FastSPICE (T-AFS), and waveform viewing and analysis (W-Edit).
Tanner Analog FastSPICE (T-AFS) licenses may be purchased as tokens; allowing the user several options on how to best allocate the tool to their workload. Transient noise analysis can also be performed by purchasing a TNA token.
Click here to learn more about T-AFS
HiPer Simulation AMS
HiPer Simulation AMS is a complete mixed signal IC design front-end. Includes schematic capture (S-Edit), analog simulation (T-Spice), digital simulation (Aldec Riviera Pro TE), mixed signal simulation (Verilog-AMS co-simulation), and waveform viewing and analysis (W-Edit).
Click here to learn more about HiPer Simulation AMS
T-Spice Pro
T-Spice Pro from Tanner EDA offers front-end designers industry-leading productivity and price-performance by combining our Schematic Capture tool (S-Edit), our Waveform viewing and analysis tool (W-Edit), and our circuit simulator (T-Spice). Additional simulation capacity can be added; by purchasing stand-alone T-Spice licenses and/or by adding T-AFS; BDA�s Analog FastSPICE.
T-Spice Power Packs
For users looking to augment their simulation capabilities and increase productivity through simultaneous simulation runs, Tanner EDA offers add-on packs of our T-Spice simulation engine. Available in units of 1, 3, 5, and 10 additional licenses, this power pack significantly bolsters productivity and reduces analysis time.
Back End Tools:
L-Edit
L-Edit combines industry-leading rendering speed with powerful features and an elegant user interface that delivers unmatched productivity in physical layout. Drawing and editing are done quickly; with fewer keystrokes and mouse clicks than other layout tools. Powerful features such as object snapping, boolean operations, and alignment tools work within an intuitive user interface so you can work efficiently and effectively.
L-Edit IC
Based on L-Edit, the fastest rendering layout editor in the market, L-Edit IC is a comprehensive physical layout and verification system that accelerates design cycles with high performance and an extremely short learning curve. L-Edit IC includes Interactive Design Rule Checking (IDRC), Node Highlighting, Schematic-Driven Layout, I/O pad cross-reference export, and our Standard Device Generator.
HiPer L-Edit DevGen
HiPer L-Edit DevGen is for engineers looking to gain high productivity by accelerating the task of creating analog building blocks such as differential pairs, current mirrors, and MOSFETs. This package couples our high-performance L-Edit IC package with HiPer DevGen. Click here to learn more about this high-performance layout acceleration capability.
HiPer L-Edit Router
HiPer L-Edit Router combines our high-performance L-Edit IC package with our SDL Router, a general area based router ideal for top-level chip assembly; offering unparalleled workflow productivity for engineers doing layout routing.
HiPer Place & Route (P&R)
HiPer Place & Router (P&R) is a right-size place and route solution for Big Analog/Little Digital mixed-signal design, offering excellent performance, ease of use, and value. HiPer P&R is optimized for analog specialty process technologies on the 90-350nm nodes, with 10-50k gates of digital logic. HiPer P&R is highly flexible, allowing the user unparalleled flexibility during every phase of the flow.
Physical Verification:
HiPer Verify
HiPer Verify from Tanner EDA is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and netlist extraction on the Windows and Linux platforms. HiPer Verify uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs. HiPer Verify can run Calibre and Dracula rule files directly from the foundry; offering the security of knowing you are running your rule files without modification or conversion, as well as the convenience of not having to perform translations.
Click here to view the HiPer Verify datasheet
External Verification Interface (EVI) for Calibre Integration
External Verification Interface (EVI) provides an interface for users of Mentor Graphics' Calibre� tool suite to use L-Edit and S-Edit for layout and schematic capture. Used in conjunction with the Calibre RVE product, you can view Calibre DRC errors, LVS results, and PEX parasitics in L-Edit and S-Edit.
EVI is also compatible with Calibre Interactive, which allows users to run DRC & LVS on L-Edit and S-Edit designs from within Calibre Interactive.
Parasitic Extraction
HiPer PX, Tanner EDA's parasitic extraction system, ensures successful RF IC tapeouts by providing accurate, simulation-ready RC models of interconnect parasitics and crosstalk.
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